Computer systems perform their arithmetic and logic functions by a processor contained therein. The processor acts as the decision maker or the brains of such computer systems. The processor is controlled by instructions and data supplied to it by the computer system, and further by microcode which is contained within the processor itself. The microcode is an instruction set implemented as a hard-wired circuit in the processor. The processor must communicate to the computer system its status, that is whether the resources of the computer are busy, waiting for data, etc. The status may be a plurality of flag bits where each flag bit may be a logical 1 or 0. The status of the system may be written to a register for storage. The register typically contains one storage element, such as a flip-flop, for each flag bit. The processor may inspect the contents of the register to find out what the status of the computer system is.
Very commonly, computer systems utilize more than one processor for performing different functions or for sharing processing functions in order to increase system throughput. One of the processors is often a master processor and the other processors are the slave processors such that the master processor controls the slave processors. Alternatively, the processors may be treated as equals so that no one processor is controlling. Regardless of the configuration, communication between the processors require that predetermined sequences, commonly known as handshaking or communication protocols, be followed in order to avoid processor conflicts. Conflicts can arise, for example, if more than one processor were to attempt to modify the same data, or were to attempt to change the system status flag bits.
A multi-processor communication interface design may consist of a shared memory and a set of registers that are controlled by the microcode. The registers are each assigned an address so that each processor may read and write to the addressed registers. The microcode protocol controls the reading and writing of the registers, during a predetermined sequence, so that one processor may set bits in the addressed registers and the other processor may reset bits in the addressed registers. This type of interface requires the registers to first be addressed under control of the microcode, and does not allow both processors to modify the bits in the registers simultaneously. An example of such an interface is given in Multi-Processor Communications Interface, IBM Technical Disclosure Bulletin, Vol. 31, No. 4, Sep. 1988.
A multi-processor configuration where a first processor performs simple boolean logic functions and a second processor performs complex arithmetic computations is described by Pavicic, et al., U.S. Pat. No. 4,215,399. In this system, the processors communicate by two flag bit registers where the first processor sets the first flag bit register to alert the second processor that a requested complex arithmetic operation is queued up. The second flag bit register is reset by the second processor to signal the first processor that the requested operation has been completed. The first processor must necessarily check the status of the second flag bit register before writing to the first flag bit register. This communication takes at least two clock cycles to complete.
Another system providing for multiple inter-processor communication is described by Cox, et al., U.S. Pat. No. 4,402,046. Here, a global communication segment common to all processors for system-wide communication is provided. The communication segment has a field containing control flags which may be set by one processor and inspected by another processor in order to control the several processor functions. Again, the different processors read and write the control flags at different times and require specific handshaking protocols to be followed which slows computer system performance.
Thus what is needed is a multi-processor system status communication interface where any or all processors may simultaneously change the status of flag bit registers without having to first address and inspect the existing contents of the flag bit registers according to a predetermined protocol.